1. Field of the Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a polysilicon gate.
2. Description of the Related Art
When integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. However, source/drain region resistances in metal oxide semiconductor (MOS) transistors simultaneously increase, and the polysilicon electrodes that form the MOS gates and wiring lines within semiconductor devices become undesirably resistive. As the resistance of the source/drain region is almost the same as the resistance of a channel in the MOS transistor, a process of self-aligned silicide (salicide) is employed to reduce the sheet resistance of the source/drain regions in order to preserve the integrity of shallow junctions between the metal layer and the MOS transistor. The salicide process is currently used in a manufacturing process of very large scale integration (VLSI) and ultra large scale integration (ULSI) device. Multilayer electrodes in which a layer of polysilicon is covered by one or more layers of metals or metal silicides are used to provide good conductivity, which improves the electrical performance of the MOS gate and the wiring line.
As the dimension of the gate becomes smaller, a narrow line effect is generated because the stress between the gate and the metal silicide layer is increased, and the nucleation site of the metal silicide layer is decreased. The quality of the metal silicide layer on the gate is thus degraded, or even an island-shaped metal silicide layer may be formed. As a consequence, the operation performance of the gate is affected.
A pre-amorphization implant (PAI) process is performed before the step of forming the silicide layer in order to reduce sheet resistance.
FIGS. 1A through 1C are schematic, cross-sectional views showing the progression of the conventional manufacturing steps for forming a self-aligned silicide.
Referring to FIG. 1A, a substrate 100 having an isolation structure 102 is provided, a gate oxide layer 104 and a polysilicon gate 106 are formed over the substrate 100, and source/drain regions 108 is formed in the substrate 100. An ion bombardment step with arsenic (As) ions is performed on the polysilicon gate 106 surface, wherein the dosage of the arsenic ions is about 1E14-1E15 ions/cm.sup.2 and the energy of the arsenic ions is about 20-40 KeV. The ion bombardment step damages the polysilicon gate 106 surface to form an amorphous silicon layer 109. The grain size of the amorphous silicon layer 109 are smaller than those of the polysilicon gate 106. Therefore, the quality of a metal silicide layer on this polysilicon gate 106 is thus increased while a self-aligned silicide process is performed sequentially.
Referring to FIG. 1B, a metallic layer 110 is formed conformal to the substrate 100 by sputtering. The metallic layer 110 reacts with the silicon of the substrate 100 and the polysilicon gate 106 surface to form a silicide layer 112 by rapid thermal processing (RTP) on the polysilicon gate 106 surface and the source/drain regions 108 surface.
Referring to FIG. 1C, the unreacted metallic layer 110 is removed by wet etching.
FIG. 2 is a schematic, cross-sectional view showing a polysilicon gate during performance of a pre-amorphization implant process.
Referring to FIG. 2, arsenic ions 116 are implanted into the polysilicon gate. While performing a pre-amorphization implant process with arsenic ions 116, the arsenic ions 116 easily pass through the polysilicon gate 106 and the gate oxide layer 104 along interface 114 between polysilicon grains into the substrate 100 because the vacancy between poly grains is large and nothing is formed in the pathway of the arsenic ions 116 to stop them. As a result, NMOS subthreshold current is increased and a subthreshold kink side-effect occurs. The quality of a device is decreased because of the effect mentioned above.